Codec design engineer-成都(J11356)

职位描述

As a key member of video codec team, you will be responsible for the implementation of video encoder/decoder related IPs. Detailed responsibilities may include, but not be limited to:

• Based on system requirements and algorithms, create micro-architecture for hardware implementation.

• RTL digital design and IP integration.

• Involve module level and system level verifications.

• Cooperate with backend team to do synthesis, and timing check, power analyses.

• Documentation and review of design specifications.

任职要求

• MS/PHD in Electrical Engineering.

• Experiences of developing video encoder/decoder related modules.

• Strong understanding of video compression algorithms, and video compression standards (AV1, H265, H264, VP9, AVS/AVS2, MPEG1/2/4, and etc.)

• Fluent in RTL design with Verilog/System Verilog, synthesis and timing closure.

• Experience with C/C++, Perl preferred.

• Experience with OVM/UVM preferred.

• Good problem solving and communication skills.