Digital Design Engineer(J11687)

职位描述

1.Responsible for the digital design of IP modules, IP subsystems, and/or for the chip top level integration

2.RTL design and verification of digital IP modules: Responsible for the implementation of your IP modules, overseeing the module-level verification in close cooperation with the verification team, and debugging failing test cases on module level and SoC top level.

3.Synthesis: deliver a timing clean design with reliable constraints

4.RTL quality checks: provide reports and waivers for LEC, LINT, and CDC checks

5.Contribute to the post-silicon validation of top and IP Subsystems

任职要求

1.Degree in Electrical Engineering or Computer Science.

2.At least 3 years of experience of hands on RTL design.

3.Working experience in advanced verification methodologies, synthesis, revision control.

4.Must have expert problem solving skills

5.Good team player with ability to work across functional teams, sites, and cultures.