Layout Design Engineer(J11639)

职位描述

• The layout designer is responsible for developing chip block level layout for automotive and power management IC parts. This includes floor planning in product definition phase, power routing, block layout design, physical size optimization, and layout verification on DRC/LVS, post layout extraction and other tasks.

• Must have strong expertise in IC layout design skills and device physics, including knowledge of critical cell/device layout, current density calculation, multiple voltage domain design and parasitic analysis.

• Interfacing with digital designer on place and routing, and integrate analog/digital block level layouts.

任职要求

• Candidate needs to hold a minimum of a B.S. degree in electrical engineering. Must have experience of block level layout design/verification.

• Must have expertise in CMOS process and have sound knowledge of MOSFET/Bipolar/passive device physics.

• Familiar with Virtuoso-XL, Calibre.