Sr. Analog Design Engineer-PLL(J11303)

职位描述

1.responsible for high-performance PLLs, DLLs, OSC, clock distribution networks design in serdes product; 2.support serdes product debug/verification, CP/FT test that everything lead to Mass-Production;

任职要求

1. MSEE with 2+ years’ experience in PLL designs; 2. Hands-on skill in key PLL sub-blocks including but not limited to: LC-VCO and Ring-VCO, PFD,CP, High-performance dividers , Low-noise bias and reference circuits design and optimize 3. Deep, fundamental understanding of PLL architectures, linear/non-linear modeling, stability analysis, and jitter/phase noise theory. 4. basic comprehension with highspeed circuit related layout knowledge; 5. Experience with high-speed simulation techniques and best practices for complex mixed-signal systems. 6. Strong problem-solving skills, innovation, and a results-oriented mindset. 7. good communication and teamwork skills.