Sr. Analog Design Engineer-PHY(J11304)

职位描述

1. responsible for analog IP design in serdes product; 2. support serdes product debug/verification, CP/FT test that everything lead to Mass-Production;

任职要求

1. MSEE with 3+ years’ experience in highspeed interface circuit design, e.g. transmitter/receiver/DFE/cdr;

2. hands-on skill in highspeed circuit design;

3. basic comprehension with highspeed circuit related layout knowledge;

4. basic comprehension with highspeed design general theory, e.g. jitter/signal integrity;

5. good team work, self-driven and motivated;

6. experience of full duplex link based serdes’s verification/debug and Mass-Production will be a big plus;