Sr. FPGA Design Engineer(J11314)
岗位信息
| 招聘单位 | 豪威 |
|---|---|
| 工作地点 | 上海市 |
| 官方更新时间 | 2025-09-01T14:48:09 |
职位描述
1. Responsible for FPGA RTL design, simulation and on board verification.
2. Responsible for frontend digital design for ASIC chips.
3. Participate in architecture definition, test and maintenance of verification platform.
4. Assist embedded FW development for SOC architecture
任职要求
1. Skillful FPGA RTL design is required. Good knowledge of digital design and system design.
2. Be experienced in FPGA IP using, such as PLL, DDR controller, transceiver.
3. Strong analytical, and problem solving skills as well as hands-on lab debugging skills.
4. Have a good knowledge of timing analysis.
5. Strong analytical, and problem solving skills as well as hands-on lab debugging skills.
6. Good communication skills, especially in technical writing and reporting.
7. 3 years+ working experience in digital design
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