Senior Staff ASIC Design Engineer

职位描述

Responsibilities

1.ISP Module / Sub-System Ownership：Own the micro-architecture and RTL of key ISP blocks or sub-systems end-to-end, from spec definition through tape-out and mass production.

2.Architecture & PPA Leadership：Drive pipeline-level dataflow, buffering strategy and interface design; lead PPA trade-offs across image quality, area, bandwidth and power; deliver architecture and μArch specifications.

3.Cross-Team Collaboration：Partner deeply with algorithm, tuning, SW / driver, DV and backend teams; align on reference-model strategy, register interfaces and convergence plans.

4.Silicon Bring-up & Productization：Lead silicon-stage image-quality debug, root-cause analysis and RTL ECOs; ensure smooth ramp to mass production.

5.Technical Leadership：Mentor mid-level and junior engineers; drive design methodology, code quality, low-power (UPF), CDC / RDC and documentation standards across the team.

任职要求

Requirements

Basic

1.BS or above in Microelectronics / EE / Communications / CS or related field.

2.5+ years of digital IC front-end experience, with at least one taped-out chip containing ISP as a key contributor or module owner.

3.Strong proficiency in Verilog / SystemVerilog and SVA.

4.Proficient with mainstream EDA tools; familiar with JasperGold / VC Formal.

Solid experience with AMBA protocols and high-bandwidth DMA design.

5.Deep understanding of the full camera imaging pipeline; able to articulate the physical meaning, image-quality impact and hardware implementation of each stage.

6.In-depth knowledge of mainstream CFA patterns and their hardware implications.

7.Strong engineering intuition for ISP bandwidth, line-buffer area and power budgets.

8.Proven ability to drive technical discussions with algorithm engineers on precision, approximation and hardware-friendliness.

Nice to Have

1.Hands-on experience with AI-ISP HW/SW co-design.

2.Experience with multi-camera fusion, bokeh, super-resolution or similar advanced imaging features.

3.Automotive ISP experience.

4.Familiarity with MIPI CSI-2 and a broad range of sensor RAW characteristics.

5.Track record of leading a module from spec to sign-off.

6.Experience with commercial ISP IP or in-house ISP development.